For silicon solar cells, the basic design constraints on surface reflection, carrier collection, recombination and parasitic resistances result in an optimum device of about 25% theoretical efficiency. A schematic of such an optimum device using a traditional geometry is shown below. Note that innovations in recent years have identified other designs that can surpass this one in efficiency.
Basic Cell Design Compromises
Bulk crystalline silicon dominates the current photovoltaic market, in part due to the prominence of silicon in the integrated circuit market. As is also the case for transistors, silicon does not have optimum material parameters. In particular, silicon's band gap is slightly too low for an optimum solar cell and since silicon is an indirect material, it has a low absorption co-efficient. While the low absorption co-efficient can be overcome by light trapping, silicon is also difficult to grow into thin sheets. However, silicon's abundance, and its domination of the semiconductor manufacturing industry has made it difficult for other materials to compete.
An optimum silicon solar cell with light trapping and very good surface passivation is about 100 µm thick. However, thickness between 200 and 500µm are typically used, partly for practical issues such as making and handling thin wafers, and partly for surface passivation reasons.
Doping of Base
A higher base doping leads to a higher Voc and lower resistance, but higher levels of doping result in damage to the crystal.
(front surface typically textured)
The front surface is textured to increase the amount of light coupled into the cell.
N-type silicon has a higher surface quality than p-type silicon so it is placed at the front of the cell where most of the light is absorbed. Thus the top of the cell is the negative terminal and the rear of the cell is the positive terminal.
A large fraction of light is absorbed close to the front surface. By making the front layer very thin, a large fraction of the carriers generated by the incoming light are created within a diffusion length of the p-n junction.
Doping Level of Emitter
The front junction is doped to a level sufficient to conduct away the generated electricity without resistive loses. However, excessive levels of doping reduces the material's quality to the extent that carriers recombine before reaching the junction.
(fingers 20 to 200 µm width, placed 1 - 5 mm apart)
The resistivity of silicon is too high to conduct away all the current generated, so a lower resistivity metal grid is placed on the surface to conduct away the current. The metal grid shades the cell from the incoming light so there is a compromise between light collection and resistance of the metal grid.
The rear contact is much less important than the front contact since it is much further away from the junction and does not need to be transparent. The design of the rear contact is becoming increasingly important as overall efficiency increases and the cells become thinner.